Automated test equipment (ATE) can be any testing assembly that performs a test on a device, semiconductor wafer or die, etc. ATE assemblies may be used to execute automated tests that quickly perform measurements and generate test results that can then be analyzed. An ATE assembly may be anything from a computer system coupled to a meter, to a complicated automated test assembly that may include a custom, dedicated computer control system and many different test instruments that are capable of automatically testing electronics parts and/or semiconductor. Automatic Test Equipment (ATE) is commonly used within the field of electrical chip manufacturing. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
In testing devices or products, e.g. after production, it is crucial to achieve among others a high product quality, an estimation of the device or product performance, a feedback concerning the manufacturing process and finally a high customer contentment. Testing devices, e.g., NAND flash packages requires some type of error capture and analysis. Usually a plurality of tests is performed in order to ensure the correct function of a device or product, commonly referred to as a device under test (“DUT”) in testing parlance. The plurality of tests is typically part of a test plan or test program that is loaded into the ATE system by the user. The test plan acts as a blueprint for running the tests on the DUTs.
Conventional ATE solutions for testing DUTs are limited because the test program controllers control tester resources in a fixed way, with fixed synchronization mechanisms between them. Conventional ATE solutions, for example, do not allow for flexibility in assigning hardware units to DUTs, and furthermore, do not allow for flexibility in keeping the hardware units synchronized between each other. This inflexibility in assigning hardware units to a DUT and keeping them synchronized in a flexible fashion results in a lack of efficient use of tester resources.